The circuit of a dc voltmeter with FET input is shown in figure. This meter decreases the quantity of power drawn from a circuit under test by increasing the input impedance using an amplifier with unity gain.
A source follower
drives an emitter follower.
The DC input is
applied to a variety attenuator to supply input voltage levels which may be
accommodated by the dc amplifier.
The input stage of the amplifier consists of FET which provides high input impedance to effectively isolate the meter circuit under measurement.
The input
impedance of a FET is bigger than 10MΩ. The bridge is balanced, in order that
for zero input the dial indicates zero.
As the emitter
follower must have some bias current present. The emitter voltage doesn't
attend volts with zero input voltage.
Thus the meter be
returned to not ground, but to a voltage which will be set to be adequate to
the quiescent point of the emitter follower output. In many practical meters
this is often made adjustable from the front panel of the meter.
Because the
setting of the zero, control affects the entire resistance serial with meter, a
calibrate control is additionally supplied.
Working:
Initially when switch is closed and therefore the supply is given to the circuit, the test terminals are short circuited.
The zero adjusting
of 2.5kΩ pot are often adjusted so as to urge the minimum reading within the
indicating meter(50µA) which amounts to balancing the bridge.
By adjusting the
10kΩ pot, full calibration is obtained.
As the input impedance
of the voltmeter is high, loading effects on the circuit under measurement is
avoided.
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